Memory circuits, whether fabricated as separate devices or embedded with other functional circuitry in an IC, present challenging testing issues. With the increased number and size of embedded memories in today's designs comes a dramatically increased possibility of defects and lower yields. IC manufacturing relies on testing at least a representative sample of manufactured devices to ensure that each of the devices reliably performs in accordance with predetermined specifications over the life of the device.
Conventional manufacturing testing of memories (e.g., random access memory (RAM), read-only memory (ROM), etc.) generally fails to detect all defects. More rigorous testing methodologies can typically detect a higher number of failures, but at a significantly increased cost. With this increased cost comes diminishing returns, since the percentage increase in cost for the added testing generally yields only a marginal increase in the number of defects that are detected. Since present manufacturing testing methodologies generally fail to detect an unacceptably high number of defective devices, memory designers are often forced to incorporate substantial robustness in their designs in order to guarantee a desired level of quality.
Many conventional IC memory testing methodologies have been employed to ensure higher quality devices. Some of these conventional testing approaches include built-in self test (BIST), level-sensitive scan design (LSSD) or scan testing, and increased, repeated probabilistic testing. BIST is a testing technique which performs circuit analysis and hardware generation for an embedded structural test methodology, and eliminates the need for external pattern sets. The digital test is typically stored in the function of a circuit included in each device, ensuring that a substantially complete digital test is applied to a memory device or circuit. BIST can quickly find many memory defects. However, shrinking geometries create more types of defects that can be extremely difficult to detect using conventional BIST methods.
In an increased, repeated probabilistic testing approach, the same test (e.g., a BIST) is typically applied to the device repeatedly. Probabilistic testing relies on random electromagnetic noise in the test environment to stress the device differently during each of several test passes, and potentially fail the device on one of the passes. However, this testing approach has only indirect and imprecise control over the noise surrounding a memory during test. In particular, such noise is virtually impossible to control on a bit-by-bit basis and is just as likely to aid an otherwise defective or weak bit, thereby masking detection of a failure. Moreover, the requirement of several repeated passes of the test increases both the time and cost of the manufacturing testing process. Another conventional testing approach is to selectively vary one or more environmental conditions, such as, but not limited to, supply voltage, temperature and clock or access rates. Often, this method aims to stress the memory device well beyond its intended operational range in order to establish a guardband or margin of operation for the device.
Conventional testing approaches generally fail to ensure a desired device quality in a cost-effective manner. There exists a need, therefore, for an improved manufacturing testing technique for efficiently testing memories.